Texas Instruments TMS320C3x - Manual (Page 224)

DMA Interrupts
7-40
7.7.3 CPU/DMA Interaction
If the DMA is not using interrupts for synchronization of transfers, it is not
affected by the processing of the CPU interrupts. Detected interrupts are
responded to by the CPU and DMA on instruction fetch boundaries only.
Since instruction fetches are halted due to pipeline conflicts or when executing
instructions in an RPTS loop, interrupts are not responded to until instruction
fetching continues. It is therefore possible to interrupt the CPU and DMA simul-
taneously with the same or different interrupts and, in effect, synchronize their
activities. For example, it may be necessary to cause a high-priority DMA
transfer that avoids bus conflicts with the CPU (that is, a transfer that makes
the DMA higher priority than the CPU). This may be accomplished by using
an interrupt that causes the CPU to trap to an interrupt routine that contains
an IDLE instruction. Then, if the same interrupt is used to synchronize DMA
transfers, the DMA transfer counter can be used to generate an interrupt and
thus return control to the CPU following the DMA transfer.
Since the DMA and CPU share the same set of interrupt flags, the DMA may
clear an interrupt flag before the CPU can respond to it. For example, if the
CPU interrupts are disabled, the DMA can respond to interrupts and thus clear
the associated interrupt flags. Figure 7–9 shows the sequence of events in the
interrupt processing for both the CPU and DMA controllers.
Figure 7–9. Parallel CPU and DMA Interrupt Processing
Does
GIE=1 and
is the interrupt
enabled in the
IE register?
Process the CPU interrupt
as shown in Figure 7–6.
Process the DMA interrupt
as shown in Figure 7–8.
No
Yes
Interrupt
Is the
interrupt enabled
in the IE
register?
No
Yes
DMA coprocessor CPU