Texas Instruments TMS320C3x - Manual (Page 70)

CPU Multiport Register File
3-7 CPU Registers
Table 3–2. Status Register Bits (Continued)
Bit Name Description Name Reset Value
CF 0 Cache freeze Enables or disables the instruction cache
Set CF = 1 to freeze the cache (cache is not updated),
including LRU stack manipulation. If the cache is
enabled (CE = 1), fetches from the cache are allowed,
but modification of the cache contents is not allowed.
Cache clearing (CC = 1) is allowed. At reset, this bit
is cleared to 0, but it is set to 1 after reset.
When CF = 0, the cache is automatically updated by
instruction fetches from external memory. Also, when
CF = 0, cache clearing (CC = 1) is allowed.
The following table summarizes the CE and CF bits:
CE
0
0
1
1
CF
0
1
0
1
Effect
Cache not enabled
Cache not enabled
Cache enabled and not frozen
Cache enabled but frozen
(cache read only)
CC 0 Cache clear CC = 1 invalidates all entries in the cache. This bit is
always cleared after it is written to, and is always read
as 0. At reset, 0 is written to this bit.
GIE 0 Global interrupt-enable If GIE = 1, the CPU responds to an enabled interrupt.
If GIE = 0, the CPU does not respond to an enabled
interrupt.
INT config 0 Interrupt configuration
(‘C32 only) Sets the external interrupt signals INT3 – INT0 for level-
or edge-triggered interrupts.
INT Config
0
1
Effect
All the external interrupts (INT3 – INT0)
are configured as level-triggered
interrupts. Multiple interrupts may be
triggered when the signal is active for
a long period of time.
All the external interrupts (INT3 – INT0)
are configured as edge-triggered inter-
rupts. Edge and duration are required
for all interrupts to be recognized.
Note: If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset.