Texas Instruments TMS320C3x - Manual (Page 269)

Memory Interface Signals
9-3 TMS320C30 and TMS320C31 External-Memory Interface
9.2 Memory Interface Signals
This section describes the differences between the ’C30 and ’C31 memory
interface signals.
9.2.1 TMS320C30 Memory Interface Signals
The TMS320C30 has two sets of control signals as follows:
- Primary bus control signals: STRB, R/W, HOLD, HOLDA, RDY
Table 9–1 lists and describes the signals.
- Expansion bus control signals: MSTRB, IOSTRB, XR/W, XRDY
Table 9–2 lists and describes the expansion bus control signals.
Access is determined by an active strobe signal (STRB, MSTRB, or IOSTRB).
When a primary bus access is performed, STRB is low. The expansion bus of
the ’C30 supports two types of accesses:
- Memory access signaled by MSTRB low. The timing for an MSTRB access
is the same as that of the STRB access on the primary bus.
- External peripheral device access is signaled by IOSTRB low.
Each of the buses (primary and expansion) has an associated control register.
These registers are memory-mapped as shown in Figure 9–1.
9.2.2 TMS320C31 Memory Interface Signals
The TMS320C31 has one set of control signals:
- Primary bus control signals: STRB, R/W, HOLD, HOLDA, RDY
STRB is low when an external bus access is performed. The primary bus
control register controls its behavior (see Section 9.3).