Texas Instruments TMS320C3x - Manual (Page 505)

Parallel ABSI and STI ABSI||STI
13-47 Assembly Language Instructions
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 0
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
Mode Bit OVM Operation is affected by OVM bit value.
Example ABSI *–AR5(1),R5
|| STI R1,*AR2 – – (IR1)
Before Instruction After Instruction
R1 00 0000 0042 R1 00 0000 0042
R5 00 0000 0000 R5 00 0000 0035
AR2 80 98FF AR2 80 98F0
AR5 80 99E2 AR5 80 99E2
IR1 0F IR1 0F
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098FF 2 8098FF 42
8099E1 0FFFFFFCB 8099E1 0FFFFFFCB
66
–53
2
66
53
–53
66
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.