Texas Instruments TMS320C3x - Manual (Page 308)

TMS320C32 Memory Overview
10-5 TMS320C32 Enhanced External Memory Interface
The PRGW status bit field of the CPU status (ST) register reflects the setting
of the PRGW pin. Figure 10–2 depicts all the bit fields of the CPU status (ST)
register.
Figure 10–2. Status Register
Б
Б
БББ
БББ
31–16 БББ
БББ
15 БББ
БББ
14 БББ
БББ
13 ББ
ББ
12 БББ
БББ
11 ББ
ББ
10 БББ
БББ
9 ББ
ББ
8 БББ
БББ
7 БББ
БББ
6 ББ
ББ
5 БББ
БББ
4 ББ
ББ
3 БББ
БББ
2 БББ
БББ
1 ББ
ББ
0 ББ
ББ Б
Б
Б
xx
PRGW
status
INT
config
БББ
Б Б Б
БББ
GIE
ББ
ББ
ББ
CC
БББ
Б Б Б
БББ
CE
ББ
ББ
ББ
CF xx
ББ
ББ
ББ
RM
БББ
Б Б Б
БББ
OVM
БББ
Б Б Б
БББ
LUF
ББ
ББ
ББ
LV
БББ
Б Б Б
БББ
UF
ББ
ББ
ББ
N
БББ
Б Б Б
БББ
Z
БББ
Б Б Б
БББ
V C
ББ
ББ
ББ Б БББ БББ
R
ÁÁÁ
R/W
ÁÁÁ
R/W
ÁÁ
R/W
ÁÁÁ
R/W
ÁÁ
R/W
БББ ББ
R/W
ÁÁÁ
R/W
ÁÁÁ
R/W
ÁÁ
R/W
ÁÁÁ
R/W
ÁÁ
R/W
ÁÁÁ
R/W
ÁÁÁ
R/W
ÁÁ
R/W
ÁÁ
Notes: 1) xx = reserved bit, read as 0
The status of the PRGW pin also affects the reset value of the physical memory
width bit fields of the STRB0 and STRB1 bus-control registers. The physical
memory width is set to 32-bit memory width if the PRGW pin is logic low after
the device reset. The physical memory width is set to 16-bit memory width if
the PRGW pin is logic high after the device reset (see Section 10.3 for more
information).
The cycle before and the cycle after changing the PRGW should not
perform a program fetch over the external memory interface.
10.2.3 Data Memory Access
The ’C32 can load and store 8-, 16-, or 32-bit data quantities from and into
memory. Because the CPU has a 32-bit architecture, the device internally
handles all 8-, 16-, or 32-bit data quantities as a 32-bit value. Hence, the external
memory interface handles the conversion between 8- and 16-bit data quantities
to the internal 32-bit representation. The external memory interface also
handles the storage of 32-, 16-, or 8-bit data quantities into 32-, 16-, or 8-bit wide
memories.
10.2.3.1 8-, 16-, or 32-Bit Integers Data Types
The ’C32 supports 8-, 16- or 32-bit integer data quantities. When 8- or 16-bit
integers are read from external memory, the value is loaded into the LSBs of
the register with the MSBs sign-extended or zero-filled. The polarity of the sign
ext/zero-fill bit field of the corresponding STRB control register controls the
sign extension or zero fill (see paragraphs 10.3.1.1 and 10.3.1.2). The 32-bit
integer data access is identical to that of the ’C30 and ’C31.