Texas Instruments TMS320C3x - Manual (Page 473)

Instruction Set Summary
13-15 Assembly Language Instructions
Table 13–8. Instruction Set Summary (Continued)
Mnemonic Operation Description
RPTB Repeat block of instructions src
→
RE
1
→
ST (RM)
Next PC
→
RS
RPTS Repeat single instruction src
→
RC
1
→
ST (RM)
Next PC
→
RS
Next PC
→
RE
SIGI Signal, interlocked Signal interlocked operation
Wait for interlock acknowledge
Clear interlock
STF Store floating-point value R n
→
Daddr
STFI Store floating-point value, interlocked R n
→
Daddr
Signal end of interlocked operation
STI Store integer Sreg
→
Daddr
STII Store integer, interlocked Sreg
→
Daddr
Signal end of interlocked operation
SUBB Subtract integers with borrow Dreg – src – C
→
Dreg
SUBB3 Subtract integers with borrow (3-operand) src1 – src2 – C
→
Dreg
SUBC Subtract integers conditionally If Dreg – src
≥
0:
[(Dreg – src) << 1] OR 1
→
Dreg
Else, Dreg << 1
→
Dreg
SUBF Subtract floating-point values R n – src
→
R n
SUBF3 Subtract floating-point values (3-operand) src1 – src2
→
R n
Legend: AR n auxiliary register n (AR7–AR0) RE repeat interrupt register
C carry bit RM repeat mode bit
C src conditional-branch addressing modes R n register address (R7–R0)
count shift value (general addressing modes) RS repeat start register
cond condition code SP stack pointer
Daddr destination memory address Sreg register address (any register)
Dreg register address (any register) ST status register
GIE global interrupt enable register src general addressing modes
N any trap vector 0–27 src1 3-operand addressing modes
PC program counter src2 3-operand addressing modes
RC repeat counter register TOS top of stack