Texas Instruments TMS320C3x - Manual (Page 609)

Parallel MPYF3 and ADDF3 MPYF3||ADDF3
13-151 Assembly Language Instructions
10 src1
×
src2, src3 + src4
11 src3
×
src1, src2 + src4
Opcode
31 24 23 16 8 7 0 15
1 0 0 0 0 0 src4 src3 P src1 src2 d1 d2
Description A floating-point multiplication and a floating-point addition are performed in
parallel. All registers are read at the beginning and loaded at the end of the
execute cycle. If one of the parallel operations (MPYF3) reads from a register
and the operation being performed in parallel (ADDF3) writes to the same reg-
ister, then MPYF3 accepts the contents of the register as input before it is mo-
dified by the ADDF3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as
register. The assignment of the source operands
srcA – srcD to the
src1 – src4 fields varies, depending on the combination of addressing modes
used, and the P field is encoded accordingly.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles 1 (see Note: Cycle Count)
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF 1 if a floating-point underflow occurs; unchanged otherwise
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 1 if a floating-point underflow occurs; 0 otherwise
N 0
Z 0
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit