Texas Instruments TMS320C3x - Manual (Page 229)

DMA Interrupts
7-45 Program Flow Control
Insert two NOP instructions immediately before the TRAP cond instruction.
One NOP is insufficient in some cases, as illustrated in the second bulleted
item, above. This eliminates the opportunity for any pipeline conflicts in the
immediately preceding instructions and enables the conditional trap
instruction to execute without delays.
- Asynchronous accesses to the interrupt flag register (IF) can cause the
’C30 silicon revision prior to 4.0 to fail to recognize and service an inter-
rupt. This may occur when an interrupt is generated and is ready to be
latched into the IF register on the same cycle that the IF is being written
to by the CPU. Note that logic operations (AND, OR, XOR) may write to
the IF register.
The logic of ’C30 silicon revision earlier than 4.0 currently gives the CPU
write priority; consequently, the asserted interrupt might be lost. This is
true if the asserted interrupt was generated internally (for example, a direct
memory access (DMA) interrupt). This situation arises as a result of a deci-
sion to poll certain interrupts or a desire to clear pending interrupts due to a
long pulse width. In the case of a long pulse width, the interrupt may be
generated after the CPU responds to the interrupt and attempts to auto-
matically clear it by the interrupt vector process.
The recommended solution is to avoid using the interrupt polling technique,
and to design the external interrupt inputs to have pulse widths between
1 and 2 instruction cycles. The alternative to strict polling is to periodically
enable and disable the interrupts that would be polled, allowing the normal
interrupt vectoring to take place; this automatically clears the interrupt flag
without affecting other interrupts. If you must clear a pending interrupt, you
should use a memory location to indicate that the interrupt is invalid. The
interrupt service routine can read that location, clear it (if the pending inter-
rupt is invalid), and return immediately. The following code fragments
show how to handle a dummy interrupt due to a long interrupt pulse: