Mpyf3||stf – Texas Instruments TMS320C3x User Manual
Page 612
MPYF3||STF
Parallel MPYF3 and STF
13-154
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
1 if a floating-point underflow occurs; 0 unchanged otherwise
LV
1 if a floating-point overflow occurs; unchanged otherwise
UF
1 if a floating-point underflow occurs; 0 otherwise
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if a floating-point overflow occurs; 0 otherwise
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
MPYF3
*–AR2(1),R7,R0
||
STF R3,*AR0
– –
(IR0)
Before Instruction
After Instruction
R0
00 0000 0000
R0
0D 09E4 A000
R3
08 6B28 0000
R3
08 6B28 0000
R7
05 7B40 0000
R7
05 7B40 0000
AR0
80 9860
AR0
80 9858
AR2
80 982B
AR2
80 982B
IR0
8
IR0
8
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
80982Ah
70C8000
80982Ah
70C8000
809860h
0
809860h
86B280000
8.82515625e+03
6.281250e+01
4.7031250e+02
1.4050e+02
4.7031250e+02
1.4050e+02
4.7031250e+02
6.281250e+01
Note:
Cycle Count
See Section 8.5.2,
Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Mode Bit