And3 – Texas Instruments TMS320C3x User Manual

Page 521

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Bitwise-Logical AND, 3-Operand

AND3

13-63

Assembly Language Instructions

Syntax

AND3

src2, src1, dst

Operation

src1 AND src2

dst

Operands

src1 3-operand addressing modes (T):

0 0

any CPU register

0 1

indirect (

disp = 0, 1, IR0, IR1)

1 0

any CPU register

1 1

indirect (

disp = 0, 1, IR0, IR1)

src2 3-operand addressing modes (T):

0 0

any CPU register

0 1

any CPU register

1 0

indirect (

disp = 0, 1, IR0, IR1)

1 1

indirect (

disp = 0, 1, IR0, IR1)

Opcode

31

24 23

16

8 7

0

15

0 0 1 0 0 0 0

dst

src1

src2

1 1

T

Description

The bitwise-logical AND between the

src1 and src2 operands is loaded into

the destination

register. The src1, src2, and dst operands are assumed to be

unsigned integers.

Cycles

1

Status Bits

These condition flags are modified only if the destination register is R7 – R0.

LUF

Unaffected

LV

Unaffected

UF

0

N

MSB of the output

Z

1 if a 0 result is generated; 0 otherwise

V

0

C

Unaffected

OVM

Operation is not affected by OVM bit value.

Mode Bit

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