Texas Instruments TMS320C3x - Manual (Page 284)

External Memory Interface Timing
9-18
Figure 9–7 illustrates a write-write-read sequence for (M)STRB active and no
wait states. The address and data written are held valid approximately one-half
cycle after (M)STRB changes.
Figure 9–7. Write-Write-Read for (M)STRB = 0
H3
H1
(X)A
(X)D
(X)R/W
(M)STRB
(X)RDY
Write data Write data Read