Texas Instruments TMS320C3x - Manual (Page 301)

External Memory Interface Timing
9-35 TMS320C30 and TMS320C31 External-Memory Interface
Figure 9–24 and Figure 9–25 illustrate the signal states when a bus is inactive
(after an IOSTRB or (M)STRB access, respectively). The strobes (STRB,
MSTRB and IOSTRB) and (X)R/W) go to 1. The address is driven with last exter-
nal bus access, and the ready signal (XRDY or RDY) is ignored.
Figure 9–24. Inactive Bus States for IOSTRB
H3
H1
XA
XD
XR/W
IOSTRB
XRDY
Write data
XRDY ignored
Bus inactive