Texas Instruments TMS320C3x - Manual (Page 539)

Branch Conditionally (Delayed) BcondD
13-81 Assembly Language Instructions
Syntax B cond D src
Operation If cond is true:
If src is in register-addressing mode (Rn, 0
≤
n
≤
27),
src
→
PC.
If src is in PC-relative mode (label or address),
displacement + PC + 3
→
PC.
Else, continue
Operands src conditional-branch addressing modes (B):
0 register
1 PC relative
Opcode
31 24 23 16 8 7 0 15
0 1 1 0 1 0 0 B 0 Register or displacement 0 1 cond
Description B cond D signifies a delayed branch that allows the three instructions after the
delayed branch to be fetched before the PC is modified. The effect is a single-
cycle branch, and the three instructions following B
cond D do not affect the
condition.
A branch is performed if the condition is true. If the src operand is expressed
in register-addressing mode, the contents of the specified register are loaded
into the PC. If the
src operand is expressed in PC-relative mode, the assembler
generates a displacement: displacement = label – (PC of branch instruction
+ 3). This displacement is stored as a 16-bit signed integer in the 16 LSBs of
the branch instruction. This displacement is added to the PC of the branch in-
struction plus 3 to generate the new PC. The ’C3x provides 20 condition codes
that you can use with this instruction (see Table 13–12 on page 13-30 for a list
of condition mnemonics, condition codes, and flags). Condition flags are
set
on the previous instruction only when the destination register is one of the ex-
tended-precision registers (R7–R0) or when one of the compare instructions
(CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit