Texas Instruments TMS320C3x - Manual (Page 672)

STF Store Floating-Point Value
13-214
Syntax STF src, dst
Operation src
→
dst
Operands src register (Rn, 0
≤
n
≤
7)
dst general addressing modes (G):
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
0 0 0 1 0 0 0 0 1 src G dst
Description The src register is loaded into the dst memory location. The src and dst oper-
ands are assumed to be floating-point numbers.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z
Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Example STF R2,@98A1h
Before Instruction After Instruction
R2 05 2C50 1900 R2 05 2C50 1900
DP 080 DP 080
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098A1h 0 8098A1h 52C5019
4.30782204e+01
4.30782204e+01
4.30782204e+01
Mode Bit