Texas Instruments TMS320C3x - Manual (Page 531)

Arithmetic Shift, 3-Operand ASH3
13-73 Assembly Language Instructions
Syntax ASH3 count, src, dst
Operation If ( count
≥
0):
src << count
→
dst
Else:
src >> |count |
→
dst
Operands count 3-operand addressing modes (T):
0 0 register (R n2, 0
≤
n2
≤
27)
0 1 register (R n2, 0
≤
n2
≤
27)
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
src 3-operand addressing modes (T):
0 0 register (R n1, 0
≤
n1
≤
27)
0 1 indirect ( disp = 0, 1, IR0, IR1)
1 0 register (R n1, 0
≤
n1
≤
27)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (R n, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 1 0 0 0 1 dst count 0 1 T src
Description The seven LSBs of the count operand are used to generate the 2s-comple-
ment shift count of up to 32 bits.
If the count operand is greater than 0, the src operand is left shifted by the value
of the count operand. Low-order bits that are shifted in are zero filled, and high-
order bits are shifted out through the status register’s C bit.
Arithmetic left shift:
C
←
src
←
0
If the count operand is less than 0, the src operand is right shifted by the abso-
lute value of the count operand. The high-order bits of the src operand are sign
extended as they are right shifted. Low-order bits are shifted out through the
C (carry) bit.
Arithmetic right shift:
sign of src
→
src
→
C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count, src, and dst operands are assumed to be signed integers.
Cycles 1