Texas Instruments TMS320C3x - Manual (Page 47)

CPU Primary Register File
2-11 Architectural Overview
The ARAU uses the 32-bit block size register (BK) in circular addressing to
specify the data block size.
The system-stack pointer (SP) is a 32-bit register that contains the address
of the top of the system stack. The SP always points to the last element pushed
onto the stack. A
push performs a preincrement; a pop performs a postdecre-
ment of the system-stack pointer. The SP is manipulated by interrupts, traps,
calls, returns, and the PUSH and POP instructions. See Section 6.10,
System
and User Stack Management, on page 6-29, for more information.
The status register (ST) contains global information relating to the state of the
CPU. Operations usually set the condition flags of the status register according
to whether the result is 0, negative, etc. These include register load and store
operations as well as arithmetic and logical functions. When the status register
is loaded, however, a bit-for-bit replacement is performed with the contents of
the source operand, regardless of the state of any bits in the source operand.
Following a load, the contents of the status register are identical to the contents
of the source operand. This allows the status register to be easily saved and
restored. See Table 3–2 on page 3-6 for a list and definitions of the status regis-
ter bits.
The CPU/DMA interrupt-enable register (IE) is a 32-bit register. The CPU
interrupt-enable bits are in locations 10– 0. The DMA interrupt-enable bits are
in locations 26–16. A 1 in a CPU/DMA interrupt-enable register bit enables the
corresponding interrupt. A 0 disables the corresponding interrupt. See Sec-
tion 3.1.8 on page 3-9 for more information.
The CPU interrupt flag register (IF) is also a 32-bit register. A 1 in a CPU
interrupt flag register bit indicates that the corresponding interrupt is set. A
0 indicates that the corresponding interrupt is not set. See Section 3.1.9 on
page 3-11 for more information.
The I/O flag register (IOF) controls the function of the dedicated external pins,
XF0 and XF1. These pins may be configured for input or output and may also
be read from and written to. See Section 3.1.10 on page 3-16 for more informa-
tion.
The repeat-counter (RC) is a 32-bit register that specifies the number of times
to repeat a block of code when performing a block repeat. When the processor
is operating in the repeat mode, the 32-bit
repeat start-address register (RS)
contains the starting address of the block of program memory to repeat, and
the 32-bit
repeat end-address register (RE) contains the ending address of the
block to repeat.