Texas Instruments TMS320C3x - Manual (Page 242)

No
execute
delay
3 PC
Pipeline Conflicts
8-6
Example 8–2. Delayed Branch
BRD THREE ; Unconditional delayed branch
MPYF ; Executed
ADD ; Executed
SUBF ; Executed
AND ; Not executed
.
.
.
THREE MPYF ; Fetched after SUBF is fetched
.
.
.
Pipeline Operation
PC Fetch Decode Read Execute
n BRD — — —
n+1 MPYF BRD — —
n+2 ADDF MPYF BRD —
n+3 SUBF ADDF MPYF BRD
3 MPYF SUBF ADDF MPYF
8.2.2 Register Conflicts
Register conflicts involve reading or writing registers used for addressing.
These conflicts occur when the pertinent register is not ready to be used. Some
conditions under which you can avoid register conflicts are discussed in Sec-
tion 8.3 on page 8-19.
The registers comprise the following three functional groups:
Group 1 This group includes auxiliary registers (AR0–AR7), index
registers (IR0, IR1), and block-size register (BK).
Group 2 This group includes the data-page pointer (DP).
Group 3 This group includes the system-stack pointer (SP).
If an instruction writes to one of these three groups, the decode unit cannot use
any register within that particular group until the write is complete, that is, until
the instruction execution is completed. In Example 8–3, an auxiliary register