Texas Instruments TMS320C3x - Manual (Page 634)

NEGF||STF Parallel NEGF and STF
13-176
Syntax NEGF src2, dst1
|| STF src3, dst2
Operation 0 – src2
→
dst1
|| src3
→
dst2
Operands src2 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
1 1 1 0 0 0 dst1 src2 dst2 1 src3 0 0 0
Description A floating-point negation and a floating-point store are performed in parallel.
All registers are read at the beginning and loaded at the end of the execute
cycle. This means that if one of the parallel operations (STF) reads from a reg-
ister and the operation being performed in parallel (NEGF) writes to the same
register, STF accepts the contents of the register as input before it is modified
by the NEGF.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF 1 if a floating-point underflow occurs; unchanged otherwise
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 1 if a floating-point underflow occurs; 0 otherwise
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit