Texas Instruments TMS320C3x - Manual (Page 617)

Multiply Integer MPYI
13-159 Assembly Language Instructions
Syntax MPYI src, dst
Operation dst
×
src
→
dst
Operands src general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst any CPU register
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 1 0 1 1 0 dst G src
Description The product of the dst and src operands is loaded into the dst register. The src
and dst operands, when read, are assumed to be 24-bit signed integers. The
result is assumed to be a 48-bit signed integer. The output to the dst register
is the 32 LSBs of the result.
Integer overflow occurs when any of the 16 MSBs of the 48-bit result differs
from the MSB of the 32-bit output value.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
OVM Operation is affected by OVM bit value. Mode Bit