Texas Instruments TMS320C3x - Manual (Page 258)

Memory Access for Maximum Performance
8-22
8.4 Memory Access for Maximum Performance
If program fetches and data accesses are performed so that the resources
being used cannot provide the necessary bandwidth, the pipeline is stalled
until the data accesses are complete. Certain configurations of program fetch
and data accesses yield conditions under which the ’C3x can achieve
maximum throughput.
Table 8–1 shows how many accesses can be performed from the different
memory spaces when it is necessary to do a program fetch and a single data
access and still achieve maximum performance (one cycle). Four cases
achieve 1-cycle maximization.
Table 8–1. One Program Fetch and One Data Access for Maximum Performance
Case No.
Primary
Bus
Accesses
Accesses From Dual
Access Internal Memory
Expansion Bus †
or
Peripheral Accesses
1 1 1 —
2 1 — 1
3 —
2 from any combination of
internal memory
—
4 — 1 1
† The expansion bus is available only on the ’C30.
Table 8–2 shows how many accesses can be performed from the different
memory spaces when it is necessary to do a program fetch and two data
accesses and still achieve maximum performance (one cycle). Six conditions
achieve this maximization.