Texas Instruments TMS320C3x - Manual (Page 583)

Load Integer Conditionally LDIcond
13-125 Assembly Language Instructions
Syntax LDI cond src, dst
Operation If cond is true:
src
→
dst,
Else:
dst is unchanged.
Operands src general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst any CPU register
Opcode
31 24 23 16 8 7 0 15
0 1 0 1 cond dst src G
Description If the condition is true, the src operand is loaded into the dst register. Other-
wise, the dst register is unchanged. Regardless of the condition, a read of the
src takes place. The dst and src operands are assumed to be signed integers.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13–12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Note that an LDIU (load integer unconditionally) instruction
is useful for loading R7–R0 without affecting the condition flags. Condition
flags are set on a previous instruction only when the destination register is one
of the extended-precision registers (R7–R0) or when one of the compare in-
structions (CMPF, CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit