Texas Instruments TMS320C3x - Manual (Page 225)

DMA Interrupts
7-41 Program Flow Control
7.7.4 TMS320C3x Interrupt Considerations
Give careful consideration to ’C3x interrupts, especially if you make modifications
to the status register when the global interrupt-enable (GIE) bit is set. This can
result in the GIE bit being erroneously set or reset as described in the following
paragraphs.
The GIE bit field of the status register is set to 0 (reset) by an interrupt. If a load
of the status register occurs simultaneously with a CPU interrupt pulse trying
to reset GIE, GIE will be reset.
Also, resetting GIE by an interrupt or TRAP instruction can cause a processing
error if any code, following within two cycles of the interrupt recognition, attempts
to read or modify the status register. For example, if the status register is being
pushed onto the stack, it will be stored incorrectly if an interrupt was acknowledged
two cycles before the store instruction.
When an interrupt signal is recognized, the ’C3x continues executing the
instructions already in the
read and decode phases in the pipeline. However,
because the interrupt is acknowledged, the GIE bit is reset to 0, and the store
instruction already in the pipeline will store the wrong status register value.
For example, if the program is like this:
...
NOP
interrupt recognized ––>LDI @V_ADDR,AR1
MPYI *AR1, R0
PUSH ST
...
POP ST
...
the PUSH ST instruction will save the ST contents in memory, which includes
GIE = 0. Since the device is expected to have GIE = 1, the POP ST instruction
will put the wrong status register value into the ST (see Table 7–9).