Texas Instruments TMS320C3x - Manual (Page 450)

DMA
Controller
12-71
Peripherals
Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued)
Cycles
(H1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate
Source
IOSTRB R1 R1 R1 R1 I R2 R2 R2 R2 I
†
IOSTRB
bus
Cw Cw
† Destination
STRB0,
STRB1, or
MSTRB
bus
W1 W1 W1 W1 W2 W2 W2 W2
(3 + Cr + 2 + Cw) T + 0.5 (T – 1)†
Cw Cw
(’C30 only)
Source
STRB bus R1 R1 R1 I R2 R2 R2 I R3 R3 R3 I
Cr Cr Cr (2 + Cr + 2 + Cw) + (2 + Cw + max[1, Cr – Cw + 1])
Destination
MSTRB
bus
W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3
(T–1)
Cw Cw Cw
Legend:
T = Number of transfers W = Single-cycle writes
Cr = Source-read wait states R n = Multicycle reads
Cw = Destination-write wait states W n = Multicycle writes
R = Single-cycle reads I = Internal register cycle
† Write followed by read incurs in one extra half-cycle.