Interlocked operations, 4 interlocked operations – Texas Instruments TMS320C3x User Manual

Page 197

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Interlocked Operations

7-13

Program Flow Control

7.4

Interlocked Operations

One of the most common parallel processing configurations is the sharing of
global memory by multiple processors. For multiple processors to access this
global memory and share data in a coherent manner, some sort of arbitration
or handshaking is necessary. This requirement for arbitration is the purpose
of the ’C3x interlocked operations.

The ’C3x provides a flexible means of multiprocessor support with five instruc-
tions, referred to as interlocked operations. Through the use of external signals,
these instructions provide powerful synchronization mechanisms. They also
guarantee the integrity of the communication and result in a high-speed opera-
tion. The interlocked-operation instruction group is listed in Table 7–2.

Table 7–2. Interlocked Operations

Mnemonic

Description

Operation

LDFI

Load floating-point value into a register,
interlocked

Signal interlocked
src

dst

LDII

Load integer into a register, interlocked

Signal interlocked
src

dst

SIGI

Signal, interlocked

Signal interlocked
Clear interlock

STFI

Store floating-point value to memory,
interlocked

Clear interlock
src

dst

STII

Store integer to memory, interlocked

Clear interlock
src

dst

The interlocked operations use the two external flag pins, XF0 and XF1. XF0
must be configured as an output pin; XF1 is an input pin. When configured in
this manner:

-

XF0 signals an interlock operation request

-

XF1 acts as an acknowledge signal for the requested interlocked operation.
In this mode, XF0 and XF1 are treated as active-low signals.

The external timing for the interlocked loads and stores is the same as for
standard loads and stores. The interlocked loads and stores may be extended
like standard accesses by using the appropriate ready signal (RDY

int

or

XRDY

int

). (RDY

int

and XRDY

int

are a combination of external ready input and

software wait states. see Chapter 9,

External Memory Interface, for more

information on ready generation.)

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