Texas Instruments TMS320C3x - Manual (Page 215)

Interrupts
7-31 Program Flow Control
7.6.3 Interrupt Prioritization
When two interrupts occur in the same clock cycle or when two previously
received interrupts are waiting to be serviced, one interrupt is serviced before
the other. The CPU handles this prioritization by servicing the interrupt with the
least priority. The priority of interrupts is handled by the CPU according to the
interrupt vector table. Priority is set according to position in the table—those with
displacements closest to the base address of the table are higher in priority.
Table 7–7 shows the priorities assigned to the reset and interrupt vectors.
Table 7–7. Reset and Interrupt Vector Priorities
Reset or
Interrupt Vector
Location
Priority Function
RESET 0h 0 External reset signal input on the RESET pin
INT0 1h 1 External interrupt on the INT0 pin
INT1 2h 2 External interrupt on the INT1 pin
INT2 3h 3 External interrupt on the INT2 pin
INT3 4h 4 External interrupt on the INT3 pin
XINT0 5h 5 Internal interrupt generated when serial-port 0 transmit buffer is empty
RINT0 6h 6 Internal interrupt generated when serial-port 0 receive buffer is full
XINT1 † 7h 7 Internal interrupt generated when serial-port 1 transmit buffer is empty
RINT1 † 8h 8 Internal interrupt generated when serial-port 1 receive buffer is full
TINT0 9h 9 Internal interrupt generated by timer0
TINT1 0Ah 10 Internal interrupt generated by timer1
DINT/
DINT0 0Bh 11 Internal interrupt generated by DMA channel 0
DINT1 ‡ 0Ch 12 Internal interrupt generated by DMA channel 1
† Reserved on ’C31 and ’C32
‡ Present on ’C32 only