Texas Instruments TMS320C3x - Manual (Page 318)

Programmable Wait States
10-15 TMS320C32 Enhanced External Memory Interface
10.4 Programmable Wait States
The ’C3x has its own internal software-configurable ready-generation capability
for each strobe. This software wait-state generator is controlled by configuring
two fields in the primary or expansion bus interface control registers. Use the
WTCNT field to specify the number of software wait states to generate and use
the SWW field to select one of the following four modes of wait-state generation:
- External RDY. Wait states are generated solely by the external RDY line
ignoring software wait states.
- WTCNT-generated RDYwtcnt. Wait states generated solely by the software
wait-state generator ignoring external RDY signals.
- Logical-AND of RDY and RDYwtcnt. Wait states generated with a logical
AND of internal and external ready signals. Both signals must occur.
- Logical-OR of RDY and RDYwtcnt. Wait states are generated with a logical
OR of internal and external ready signals. Either signal can generate ready.
The four modes are used to generate the internal ready signal, RDY
int
, that
controls accesses. As long as RDY
int
= 1, the current external access is
delayed. When RDY
int
= 0, the current access completes. Since the use of
programmable wait states for both external interfaces is identical, only the
primary bus interface is described in the following paragraphs.
RDY
wtcnt
is an internally generated ready signal. When an external access is
begun, the value in WTCNT is loaded into a counter. WTCNT can be any value
from 0 through 7. The counter is decremented every H1/H3 clock cycle until
it becomes 0. Once the counter is set to 0, it remains set to 0 until the next
access. While the counter is nonzero, RDY
wtcnt
= 1. While the counter is 0,
RDY
wtcnt
= 0.
Table 10–3 shows the truth table for each value of SWW and the different
combinations of RDY, RDY
wtcnt
, and RDY
int
.
Note:
At reset, the ‘C3x is programmed with seven wait states for each external
memory access. These wait states are inserted to ensure the system can func-
tion with slow memories. To maximize system performance when accessing
external memories, you need to decrease the number of wait states.
After changing wait states, up to three instructions will be fetched before the
change in the wait-state occurs.