Texas Instruments TMS320C3x - Manual (Page 407)

Serial Ports
12-28
12.2.6 Receive/Transmit Timer-Period Register
The receive/transmit timer-period register is a 32-bit register (see Figure 12–18).
Bits 15–0 are the timer transmit period, and bits 31–16 are the receive period.
Each register specifies the period of the timer and is
cleared to 0 at reset.
Figure 12–18. Receive/Transmit Timer-Period Register
31 16
15 0
Receive period
Transmit period
Note: All bits are read/write.
12.2.7 Data-Transmit Register
When the data-transmit register (DXR) is loaded, the transmitter loads the word
into the transmit-shift register (XSR), and the bits are shifted out. The delay from
a write to DXR until an FSX occurs (or can be accepted) is two CLKX cycles.
The word is not loaded into the shift register until the shifter is empty. When DXR
is loaded into XSR, the XRDY bit is set, specifying that the buffer is available
to receive the next word. Four tap points within the transmit-shift register are
used to transmit the word. These tap points correspond to the four-data word
sizes and are illustrated in Figure 12–19. The shift is a left-shift (LSB to MSB)
with the data shifted out of the MSB corresponding to the appropriate tap point.
Figure 12–19. Transmit Buffer Shift Operation
31 24 23 16 15 8 7 0
32-bit word tap 24-bit word tap 16-bit word tap 8-bit word tap
←
Shift direction
←
12.2.8 Data-Receive Register
When serial data is input, the receiver shifts the bits into the receive-shift register
(RSR). When the specified number of bits are shifted in, the data-receive register
(DRR) is loaded from RSR, and the RRDY status bit is set. The receiver is double-
buffered. If the DRR has not been read and the RSR is full, the receiver is frozen.
New data coming into the DR pin is ignored. The receive shifter does not write over
the DRR. The DRR must be read to allow new data in the RSR to be transferred
to the DRR. When a write to DRR occurs at the same time that an RSR-to-DRR
transfer takes place, the RSR-to-DRR transfer has priority.