Cmpf3 – Texas Instruments TMS320C3x User Manual
Page 548
CMPF3
Compare Floating-Point Value, 3-Operand
13-90
Syntax
CMPF3
src2, src1
Operation
src1 – src2
Operands
src1 3-operand addressing modes (T):
0 0
register (R
n1, 0
≤
n1
≤
7)
0 1
indirect (
disp = 0, 1, IR0, IR1)
1 0
register (R
n1, 0
≤
n1
≤
7)
1 1
indirect (
disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0
register (R
n2, 0
≤
n2
≤
7)
0 1
register (R
n2, 0
≤
n2
≤
7)
1 0
indirect (
disp = 0, 1, IR0, IR1)
1 1
indirect (
disp = 0, 1, IR0, IR1)
Opcode
31
24 23
16
8 7
0
15
0 0 1 0
0 1 1 0
T
src2
0
0
0
0
0
0
src1
Description
The
src2 operand is subtracted from the src1 operand. The result is not loaded
into any register, which allows for nondestructive compares. The
src1 and src2
operands are assumed to be floating-point numbers. Although this instruction
has only two operands, it is designated as a 3-operand instruction because op-
erands are specified in the 3-operand format.
Cycles
1
Status Bits
These condition flags are modified for all destination registers (R27 – R0).
LUF
1 if a floating-point underflow occurs; unchanged otherwise
LV
1 if a floating-point overflow occurs; unchanged otherwise
UF
1 if a floating-point underflow occurs; 0 otherwise
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if a floating-point overflow occurs; 0 otherwise
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Mode Bit