Texas Instruments TMS320C3x - Manual (Page 96)

Reset/Interrupt/Trap Vector Map
4-14
4.2 Reset/Interrupt/Trap Vector Map
The addresses for the reset, interrupt, and trap vectors are 00h–3Fh, as shown
in Figure 4–7 and Figure 4–8. The reset vector contains the address of the reset
routine.
- ’C30 and ’C31 Microprocessor and Microcomputer Modes
In the microprocessor mode of the ’C30 and ’C31 and the microcomputer
mode of the ’C30, the reset interrupt and trap vectors stored in locations
0h–3Fh are the addresses of the starts of the respective reset, interrupt,
and trap routines. For example, at reset, the content of memory location
00h (reset vector) is loaded into the PC, and execution begins from that
address (see Figure 4–8 on page 4-16).
- ’C31 Microcomputer/Boot-Loader Mode
In the microcomputer/boot-loader mode of the ’C31, the interrupt and trap
vectors stored in locations 809FC1h–809FFFh are
branch instructions to
the start of the respective interrupt and trap routines (see Figure 4–9 on
page 4-17).
- ’C32 Microprocessor and Microcomputer/Boot-Loader Mode
The ’C32 has a user-relocatable interrupt-trap vector table. The interrupt-
trap vector table must start on a 256-word boundary. The starting location is
programmed through the interrupt-trap table pointer (ITTP) bit field in the
CPU interrupt flag (IF) register. See Section 3.1.9.1,
Interrupt-Trap Table
Pointer (ITTP), on page 3-14. The reset vector is stored at location 0h in
microprocessor mode.