Texas Instruments TMS320C3x - Manual (Page 55)

External Memory Interface
2-19 Architectural Overview
2.7 External Memory Interface
The ’C30 provides two external interfaces: the primary bus and the expansion
bus. The ’C31 provides one external interface: the primary bus. The ’C32 pro-
vides one enhanced external interface with three independent multi-function
strobes. These buses consist of a 32-bit data bus and a set of control signals. The
primary and enhanced memory buses have a 24-bit address bus, whereas the
expansion bus has a 13-bit address bus. These buses address external program/
data memory or I/O space. The buses also have external RDY signals for wait-
state generation. You can insert additional wait states under software control.
Chapter 9,
External Memory Interface, covers external bus operation.
The ’C3x family was designed for 32-bit instructions and 32-bit data operations.
This architecture has many advantages, including a high degree of parallelism
and provisions for a C compiler. However, the ’C30 and ’C31 require a 32-bit-wide
external memory even when the data requires only 8- or 16-bit-wide memories.
The ’C32 enhanced external memory interface overcomes this limitation by pro-
viding the flexibility to address 8-, 16-, or 32-bit data independently of the exter-
nal memory width. In this way, the chip count and the size of external memory
is reduced. The number of memory chips can be further reduced by the ’C32’s
ability to allow code execution from 16- or 32-bit-wide memories. The ’C32
memory interface also reduces the total amount of RAM by allowing the physical
data memory to be 8, 16, or 32 bits wide. Internally, the ’C32 has a 32-bit archi-
tecture. So you can treat the ’C32 as a 32-bit device regardless of the physical
external memory width. The external memory interface handles the conversion
between external memory width and ’C32 internal 32-bit architecture.
2.7.1 TMS320C32 16- and 32-Bit Program Memory
The ’C32 executes code from either 16- or 32-bit-wide memories. When
connected to 32-bit memories, ‘C32 program execution is identical to that
of the ’C31. When connected to 16-bit zero wait-state memory, the ’C32
takes two instruction cycles to fetch a single 32-bit instruction. During the
first cycle, the ’C32 fetches the lower 16 bits. During the second cycle, the
’C32 fetches the upper 16 bits and concatenates them with the previously
fetched lower 16 bits. This process occurs entirely within the memory inter-
face and is transparent to you. An external pin, PRGW, dictates the external
program memory width.