Texas Instruments TMS320C3x - Manual (Page 105)

Instructions may
be fetched before
cache is enabled
or frozen.
Cache cleared
Instructions may
be fetched before
cache cleared.
Instruction Cache
4-23 Memory and the Instruction Cache
Table 4–1. Combined Effect of the CE and CF Bits
CE CF Effect
0 0 Cache not enabled
0 1 Cache not enabled
1 0 Cache enabled and not frozen
1 1 Cache enabled and frozen
When the CE or CF bits of the CPU status register are modified, the following
four instructions may or may not be fetched from the cache or external memory
(see Example 4–1).
When the CC bit of the CPU status register is modified, the following five instruc-
tions may or may not be fetched from the cache before the cache is cleared (see
Example 4–1).
Example 4–1. Pipeline Effects of Modifying the Cache Control Bits
Pipeline Operation
Cycle Fetch Decode Read Execute
n LDI 1000h, ST
n+1 LDI 1h, R1 LDI 1000h, ST
n+2 LDI 2h, R2 LDI 1h, R1 LDI 1000h, ST
n+3 LDI 3h, R3 LDI 2h, R2 LDI 1h, R1 LDI 1000h, ST
n+4 LDI 4h, R4 LDI 3h, R3 LDI 2h, R2 LDI 1h, R1
n+5 LDI 5h, R5 LDI 4h, R4 LDI 3h, R3 LDI 2h, R2
n+6 LDI 5h, R5 LDI 4h, R4 LDI 3h, R3
n+7 LDI 5h, R5 LDI 4h, R4
n+8 LDI 5h, R5