Document Outline

• IMPORTANT NOTICE
• Read This First
  • About This Manual
  • Notational Conventions
  • Information About Cautions
  • Related Documentation From Texas Instruments
  • References
  • If You Need Assistance
  • Trademarks
• Contents
• Figures
• Tables
• Examples
• Introduction
  • TMS320C3x Devices
    • TMS320C3x Key Specifications
    • TMS320C30
    • TMS320C31 and TMS320LC31
    • TMS320C32
  • Typical Applications
• Architectural Overview
  • Overview
  • Central Processing Unit (CPU)
    • Floating-Point/Integer Multiplier
    • Arithmetic Logic Unit (ALU) and Internal Buses
    • Auxiliary Register Arithmetic Units (ARAUs)
  • CPU Primary Register File
  • Other Registers
  • Memory Organization
    • RAM, ROM, and Cache
    • Memory Addressing Modes
  • Internal Bus Operation
  • External Memory Interface
    • TMS320C32 16- and 32-Bit Program Memory
    • TMS320C32 8-, 16-, and 32-Bit Data Memory
  • Interrupts
  • Peripherals
    • Timers
    • Serial Ports
  • Direct Memory Access (DMA)
  • TMS320C30, TMS320C31, and TMS320C32 Differences
• CPU Registers
  • CPU Multiport Register File
    • Extended-Precision Registers (R7–R0)
    • Auxiliary Registers (AR7–AR0)
    • Data-Page Pointer (DP)
    • Index Registers (IR0, IR1)
    • Block Size (BK) Register
    • System-Stack Pointer (SP)
    • Status (ST) Register
    • CPU/DMA Interrupt-Enable (IE) Register
    • CPU Interrupt Flag (IF) Register
      • Interrupt-Trap Table Pointer (ITTP)
    • I/O Flag (IOF) Register
    • Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers
  • Other Registers
    • Program-Counter (PC) Register
    • Instruction Register (IR)
  • Reserved Bits and Compatibility
• Memory and the Instruction Cache
  • Memory
    • Memory Maps
      • TMS320C30 Memory Map
      • TMS320C31 Memory Map
      • TMS320C32 Memory Map
    • Peripheral Bus Memory Map
      • TMS320C30 Peripheral Bus Memory Map
      • TMS320C31 Peripheral Bus Memory Map
      • TMS320C32 Peripheral Bus Memory Map
  • Reset/Interrupt/Trap Vector Map
  • Instruction Cache
    • Instruction-Cache Architecture
    • Instruction-Cache Algorithm
    • Cache Control Bits
• Data Formats and Floating-Point Operation
  • Integer Formats
    • Short-Integer Format
    • Single-Precision Integer Format
  • Unsigned-Integer Formats
    • Short Unsigned-Integer Format
    • Single-Precision Unsigned-Integer Format
  • Floating-Point Formats
    • Short Floating-Point Format
    • TMS320C32 Short Floating-Point Format for External 16-Bit Data
    • Single-Precision Floating-Point Format
    • Extended-Precision Floating-Point Format
    • Determining the Decimal Equivalent of a TMS320C3x Floating-Point Format
    • Conversion Between Floating-Point Formats
  • Floating-Point Conversion (IEEE Std. 754)
    • Converting IEEE Format to 2s-Complement TMS320C3x Floating-Point Format
      • IEEE-to-TMS320C3x Floating-Point Format Conversion
    • Converting 2s-Complement TMS320C3x Floating-Point Format to IEEE Format
      • TMS320C3x-to-IEEE Floating-Point Format Conversion
  • Floating-Point Multiplication
  • Floating-Point Addition and Subtraction
  • Normalization Using the NORM Instruction
  • Rounding (RND Instruction)
  • Floating-Point to Integer Conversion (FIX Instruction)
  • Integer to Floating-Point Conversion (FLOAT Instruction)
  • Fast Logarithms on a Floating-Point Device
    • Example of Fast Logarithm on a Floating-Point Device
    • Points to Consider
• Addressing Modes
  • Addressing Types
  • Register Addressing
  • Direct Addressing
  • Indirect Addressing
  • Immediate Addressing
  • PC-Relative Addressing
  • Circular Addressing
  • Bit-Reversed Addressing
  • Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools
  • System and User Stack Management
    • System-Stack Pointer
    • Stacks
    • Queues
• Program Flow Control
  • Repeat Modes
    • Repeat-Mode Control Bits
    • Repeat-Mode Operation
    • RPTB Instruction
    • RPTS Instruction
    • Repeat-Mode Restrictions
    • RC Register Value After Repeat Mode Completes
    • Nested Block Repeats
  • Delayed Branches
  • Calls, Traps, and Returns
  • Interlocked Operations
    • Interrupting Interlocked Operations
    • Using Interlocked Operations
    • Pipeline Effects of Interlocked Instructions
  • Reset Operation
  • Interrupts
    • TMS320C30 and TMS320C31 Interrupt Vector Table
    • TMS320C32 Interrupt Vector Table
    • Interrupt Prioritization
    • CPU Interrupt Control Bits
    • Interrupt Flag Register Behavior
    • Interrupt Processing
    • CPU Interrupt Latency
    • External Interrupts
  • DMA Interrupts
    • DMA Interrupt Control Bits
    • DMA Interrupt Processing
    • CPU/DMA Interaction
    • TMS320C3x Interrupt Considerations
    • TMS320C30 Interrupt Considerations
  • Traps
    • Initialization of Traps and Interrupts
    • Operation of Traps
  • Power Management Modes
    • IDLE2 Power-Down Mode
    • LOPOWER
• Pipeline Operation
  • Pipeline Structure
  • Pipeline Conflicts
    • Branch Conflicts
    • Register Conflicts
    • Memory Conflicts
      • Program Wait
      • Program Fetch Incomplete
      • Execute Only
      • Hold Everything
  • Resolving Register Conflicts
  • Memory Access for Maximum Performance
  • Clocking Memory Accesses
    • Program Fetches
    • Data Loads and Stores
      • 2-Operand Instruction Memory Accesses
      • 3-Operand Instruction Memory Reads
      • Operations with Parallel Stores
      • Parallel Multiplies and Adds
• TMS320C30 and TMS320C31 External-Memory Interface
  • Overview
  • Memory Interface Signals
    • TMS320C30 Memory Interface Signals
    • TMS320C31 Memory Interface Signals
  • Memory Interface Control Registers
    • Primary-Bus Control Register
    • Expansion-Bus Control Register
  • Programmable Wait States
  • Programmable Bank Switching
  • External Memory Interface Timing
    • Primary-Bus Cycles
    • Expansion-Bus I/O Cycles
    • Hold Cycles
• TMS320C32 Enhanced External Memory Interface
  • TMS320C32 Memory Features
  • TMS320C32 Memory Overview
    • External Memory Interface Overview
    • Program Memory Access
    • Data Memory Access
      • 8-, 16-, or 32-Bit Integers Data Types
      • 16- or 32-Bit Floating-Point Data Types
  • Configuration
    • External Interface Control Registers
      • STRB0\ Control Register
      • STRB1\ Control Register
      • IOSTRB\ Control Register
    • Using Physical Memory Width and Data-Type Size Fields
  • Programmable Wait States
  • Programmable Bank Switching
  • 32-Bit-Wide Memory Interface
    • Case 1: 32-Bit-Wide Memory With 8-Bit Data-Type Size
    • Case 2: 32-Bit-Wide Memory With 16-Bit Data-Type Size
    • Case 3: 32-Bit-Wide Memory With 32-Bit Data-Type Size
  • 16-Bit-Wide Memory Interface
    • Case 4: 16-Bit-Wide Memory With 8-Bit Data-Type Size
    • Case 5: 16-Bit-Wide Memory With 16-Bit Data-Type Size
    • Case 6: 16-Bit-Wide Memory with 32-Bit Data-Type Size
  • 8-Bit-Wide Memory Interface
    • Case 7: 8-Bit-Wide Memory With 8-Bit Data-Type Size
    • Case 8: 8-Bit Wide Memory With 16-Bit Data-Type Size
    • Case 9: 8-Bit-Wide Memory With 32-Bit Data-Type Size
  • External Ready Timing Improvement
  • Bus Timing
    • STRB0\ and STRB1\ Bus Cycles
    • IOSTRB\ Bus Cycles
    • Inactive Bus States
• Using the TMS320C31 and TMS320C32 Boot Loaders
  • TMS320C31 Boot Loader
    • TMS320C31 Boot-Loader Description
    • TMS320C31 Boot-Loader Mode Selection
    • TMS320C31 Boot-Loading Sequence
    • TMS320C31 Boot Data Stream Structure
      • Examples of External TMS320C31 Memory Loads
      • Serial-Port Loading
    • Interrupt and Trap-Vector Mapping
    • TMS320C31 Boot-Loader Precautions
  • TMS320C32 Boot Loader
    • TMS320C32 Boot-Loader Description
    • TMS320C32 Boot-Loader Mode Selection
    • TMS320C32 Boot-Loading Sequence
    • TMS320C32 Boot Data Stream Structure
    • Boot-Loader Hardware Interface
    • TMS320C32 Boot-Loader Precautions
• Peripherals
  • Timers
    • Timer Pins
    • Timer Control Registers
    • Timer Global-Control Register
    • Timer-Period and Counter Registers
    • Timer Pulse Generation
    • Timer Operation Modes
      • CLKSRC = 1 and FUNC = 0
      • CLKSRC = 1 and FUNC = 1
      • CLKSRC = 0 and FUNC = 0
      • CLKSRC = 0 and FUNC = 1
    • Using TCLKx as General-Purpose I/O Pins
    • Timer Interrupts
    • Timer Initialization/Reconfiguration
  • Serial Ports
    • Serial-Port Global-Control Register
    • FSX/DX/CLKX Port-Control Register
    • FSR/DR/CLKR Port-Control Register
    • Receive/Transmit Timer-Control Register
    • Receive/Transmit Timer-Counter Register
    • Receive/Transmit Timer-Period Register
    • Data-Transmit Register
    • Data-Receive Register
    • Serial-Port Operation Configurations
    • Serial-Port Timing
      • Continuous Transmit and Receive Modes
      • Handshake Mode
    • Serial-Port Interrupt Sources
    • Serial-Port Functional Operation
      • Fixed Data-Rate Timing Operation
      • Variable Data-Rate Timing Operation
    • Serial-Port Initialization/Reconfiguration
    • TMS320C3x Serial-Port Interface Examples
      • Handshake Mode Example
      • CPU Transfer With Serial Port Transmit Polling Method
      • DMA Transfer With Serial Port Interrupt
      • Serial Analog Interface Chips Interface Example
      • Serial Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Interface Example
  • DMA Controller
    • DMA Functional Description
      • TMS320C30 and TMS320C31 DMA Controller
      • TMS320C32 Two-Channel DMA Controller
    • DMA Basic Operation
    • DMA Registers
      • DMA Global-Control Register
      • Destination-Address and Source-Address Registers
      • Transfer-Counter Register
    • CPU/DMA Interrupt-Enable Register
    • TMS320C32 DMA Internal Priority Schemes
      • Fixed Priority Scheme
      • Rotating Priority Scheme
    • CPU and DMA Controller Arbitration
    • DMA and Interrupts
      • Interrupts and Synchronization of DMA Channels
    • DMA Memory Transfer Timing
      • Single DMA Memory Transfer Timing
    • DMA Initialization/Reconfiguration
    • Hints for DMA Programming
    • DMA Programming Examples
• Assembly Language Instructions
  • Instruction Set
    • Load and Store Instructions
    • 2-Operand Instructions
    • 3-Operand Instructions
    • Program-Control Instructions
    • Low-Power Control Instructions
    • Interlocked-Operations Instructions
    • Parallel-Operations Instructions
    • Illegal Instructions
  • Instruction Set Summary
  • Parallel Instruction Set Summary
  • Group Addressing Mode Instruction Encoding
    • General Addressing Modes
    • 3-Operand Addressing Modes
    • Parallel Addressing Modes
    • Conditional-Branch Addressing Modes
  • Condition Codes and Flags
  • Individual Instructions
    • Symbols and Abbreviations
    • Optional Assembler Syntax
    • Individual Instruction Descriptions
      • EXAMPLE
      • ABSF
      • ABSF||STF
      • ABSI
      • ABSI||STI
      • ADDC
      • ADDC3
      • ADDF
      • ADDF3
      • ADDF3||STF
      • ADDI
      • ADDI3
      • ADDI3||STI
      • AND
      • AND3
      • AND3||STI
      • ANDN
      • ANDN3
      • ASH
      • ASH3
      • ASH3||STI
      • Bcond
      • BcondD
      • BR
      • BRD
      • CALL
      • CALLcond
      • CMPF
      • CMPF3
      • CMPI
      • CMPI3
      • DBcond
      • DBcondD
      • FIX
      • FIX||STI
      • FLOAT
      • FLOAT||STF
      • IACK
      • IDLE
      • IDLE2
      • LDE
      • LDF
      • LDFcond
      • LDFI
      • LDF||LDF
      • LDF||STF
      • LDI
      • LDIcond
      • LDII
      • LDI||LDI
      • LDI||STI
      • LDM
      • LDP
      • LOPOWER
      • LSH
      • LSH3
      • LSH3||STI
      • MAXSPEED
      • MPYF
      • MPYF3
      • MPYF3||ADDF3
      • MPYF3||STF
      • MPYF3||SUBF3
      • MPYF3||ADDF3
      • MPYF3||SUBF3
      • MPYI
      • MPYI3
      • MPYI3||ADDI3
      • MPYI3||STI
      • MPYI3||SUBI3
      • NEGB
      • NEGF
      • NEGF||STF
      • NEGI
      • NEGI||STI
      • NOP
      • NORM
      • NOT
      • NOT||STI
      • OR
      • OR3
      • OR3||STI
      • POP
      • POPF
      • PUSH
      • PUSHF
      • RETIcond
      • RETScond
      • RND
      • ROL
      • ROLC
      • ROR
      • RORC
      • RPTB
      • RPTS
      • SIGI
      • STF
      • STFI
      • STF||STF
      • STI
      • STII
      • STI||STI
      • SUBB
      • SUBB3
      • SUBC
      • SUBF
      • SUBF3
      • SUBF3||STF
      • SUBI
      • SUBI3
      • SUBI3||STI
      • SUBRB
      • SUBRF
      • SUBRI
      • SWI
      • TRAPcond
      • TSTB
      • TSTB3
      • XOR
      • XOR3
      • XOR3||STI
• Instruction Opcodes
• TMS320C31 Boot Loader Source Code
• TMS320C32 Boot Loader Source Code
  • Boot-Loader Source Code Description
  • Boot-Loader Source Code Listing
• Glossary
• Index