Yaskawa MP920 User's Manual Design - Manual (Page 433)

9 Multi-CPU System
9.1.2 Operation
9-6
„ CPU Module Registers and Shared Memory
By default, the CPU Module 1 and CPU Module 2 data memory areas (M, S, D, #, I, O, and
C registers) are independent from each other. M registers, however, can be set as shared
memory to allow each CPU Module to read the specified M registers in the other CPU Mod-
ule. Refer to 5 Settings on the Common Memory Assignment Tab Page of the System Config-
uration Window
in 9.2.2 Setup Procedure Using the MPE720 for details.
„ Controlling Optional Modules
In an MP920 Multi-CPU System, the CPU Module that initializes an Optional Module and
synchronizes processing is called the Control CPU Module. The other CPU Module is called
the Sub CPU Module. The Control CPU Module must be set for each Optional Module in
the Module Configuration Definition Window. Which CPU Module (CPU Module 1 or CPU
Module 2) is to be specified as the Control CPU Module depends on the Optional Modules
as described next.
Motion Modules
For any Motion Module (SVA, SVB, or PO), set CPU Module 1 as the Control CPU Module
* 1
.
By setting CPU Module 1 as the Control CPU Module, a Motion Module operates in syn-
chronization with CPU Module 1. Therefore, access the Motion Module from the Control
CPU Module (CPU Module 1).
If the previously described synchronized scans have been set, it is possible to access the
Motion Module from the Sub CPU Module (CPU Module 2). In this case, do not access the
Motion Module immediately after the start of scanning
* 2
and assign one CPU Module to
access each axis to avoid malfunctions caused by conflicts between multiple accesses.
* 1. If the Control CPU Module of the Motion Module is inadvert-
ently set to CPU Module 2, initialization and synchronized pro-
cessing will not be performed and normal operation may not be
possible.
* 2. For the default setting, both CPU Module 1 and CPU Module 2
are synchronized on the high-speed scans as shown in Fig. 9.5. A
Motion Module, however, executes commands at the input and
output timing of the Control CPU Module (CPU Module 1) and its
execution is not synchronized with the Sub CPU Module (CPU
Module 2). Accordingly, when controlling a Motion Module from
the Sub CPU Module, do not access the Motion Module from the
Sub CPU Module
immediately after the start of scanning .