Digi NS9750 - Manual (Page 101)

w w w . d i g i e m b e d d e d . c o m 7 7
W o r k i n g w i t h t h e C P U
Figure 23 shows the format of the Context ID register (Rd) transferred during this
operation.
Figure 23: Context ID register format
R14 register
Accessing (reading or writing) this register is reserved.
R15: Test and debug register
Register R15 to provides device-specific test and debug operations in ARM926EJ-S
processors. Use of this register currently is reserved.
Jazelle (Java)
The ARM926EJ-S processor has ARM’s embedded Jazelle Java acceleration hardware
in the core. Java offers rapid application development to software engineers.
The ARM926EJ-S processor core executes an extended ARMv5TE instruction set, which
includes support for Java byte code execution (ARMv5TEJ). An ARM optimized Java
Virtual Machine (JVM) software layer has been written to work with the Jazelle
hardware. The Java byte code acceleration is accomplished by the following:
Hardware, which directly executes 80% of simple Java byte codes.
Software emulation within the ARM-optimized JVM, which addresses the
remaining 20% of the Java byte codes.
31 0
Context identifier