Digi NS9750 User Manual
Page 240
R e g i s t e r s
2 1 6
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Dynamic Memory Last Data Out to Active Time register
Address: A070 003C
The Dynamic Memory Last Data Out to Active Time register allows you to program the
last-data-out to active command time, t
APR
. It is recommended that this register be
modified during system initialization, or when there are no current or outstanding
transactions. Wait until the memory controller is idle, then enter low-power or
disabled mode. This value normally is found in SDRAM datasheets as t
APR
.
Note:
The Dynamic Memory Last Data Out to Active Time register is used for all
four dynamic memory chip selects. The worst case value for all chip
selects must be programmed.
Register bit assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
APR
Last-data-out to active command time (t
APR
)
0x0–0xE
n+1 clock cycles, where the delay is in
CLK
cycles.
0xF
16 clock cycles (reset value on
reset_n
)
Table 147: Dynamic Memory Last Data Out to Active Time register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
APR