Digi NS9750 - Manual (Page 140)

F e a t u r e s
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Features
The memory controller provides these features:
AMBA 32-bit AHB compliancy.
Dynamic memory interface support including SDRAM and JEDEC low-power
SDRAM.
Asynchronous static memory device support including RAM, ROM, and Flash,
with and without asynchronous page mode.
Can operate with cached processors with copyback caches.
Can operate with uncached processors.
Low transaction latency.
Read and write buffers to reduce latency and improve performance,
particularly for uncached processors.
8-bit, 16-bit, and 32-bit wide static memory support.
16-bit and 32-bit wide chip select SDRAM memory support.
Static memory features, such as:
–
Asynchronous page mode read
–
Programmable wait states
–
Bus turnaround delay
–
Output enable and write enable delays
–
Extended wait
Power-saving modes that dynamically control SDRAM
clk_en
.
Dynamic memory self-refresh mode supported by a power management unit
(PMU) interface or by software.
Controller supports 2K, 4K, and 8K row address synchronous memory parts;
that is, typical 512 MB, 256 MB, and 16 Mb parts with 8, 16, or 32 DQ bits
per device.
A separate AHB interface to program the memory controller. This enables
the memory controller registers to be situated in memory with other system
peripheral registers.
Locked AHB transaction support.