Digi NS9750 - Manual (Page 295)

w w w . d i g i e m b e d d e d . c o m 2 7 1
S y s t e m C o n t r o l M o d u l e
System attributes
System software can configure these NS9750 system attributes:
Little endian/big endian mode
Watchdog timer enable
Watchdog timeout generates IRQ/FIQ/RESET
Watchdog timeout interval
Enable/disable ERROR response for misaligned data access
System module clock enables
Enable access to internal registers in USER mode
Bus monitor enable
Bus monitor timeout interval
Bus arbiter timer enable
Bus arbiter timeout period
Bus arbiter timeout response (IRQ/FIQ/RESET)
Bus bandwidth configuration
Wake-up processor enable
PLL configuration
PLL operating parameters are initialized on a powerup hardware reset. Software
reads the powerup hardware settings by reading the status fields in the PLL
Configuration register (see "PLL Configuration register" on page 299). Software can
change the PLL configuration after a powerup reset by writing to the appropriate
SW
field in the PLL Configuration register (see "PLL Configuration register," beginning on
page 299). Once the new settings have been written, the PLL SW change bit must be
set (see page 300). The PLL settings then are written to the PLL, and the system is
reset.
The PLL can be configured at powerup by placing pulldowns on the external memory
address pins. NS9750 provides internal pullups to produce a default configuration; see
"Bootstrap initialization" on page 272 for information about the powerup
configuration.