Digi NS9750 - Manual (Page 629)

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S e r i a l C o n t r o l M o d u l e : U A R T
receiver waits for the start bit. When it finds the high-to-low transition, the receiver
counts 8 sample times and uses this point as the bit-center for all remaining bits in
the UART frame. Each bit-time is 16 clock ticks apart.
When the UART is not transmitting data, it transmits a continuous stream of ones —
referred to as the IDLE condition. When data transmission begins, the transmitter
sends the start bit and the receiver is enabled.
You can configure the UART to perform the following functions:
Enable the transmitter using the CTS handshaking signal. In this mode, the
transmitter cannot start a new UART data frame unless CTS is active. If CTS
is dropped anywhere in the middle of a UART data frame, the current
character is completed and the next character is stalled.
Signal its receiver FIFO status using the RTS handshaking signal. When the
receive FIFO has only four characters of available space, the RTS signal is
dropped. The RTS and CTS pairs can be used for hardware flow control.
FIFO management
Data flow between a serial controller and memory occurs through the FIFO blocks
within each serial controller module. Each serial controller provides both a 32-byte
transmit FIFO and a 32-byte receive FIFO. Each FIFO is arranged as eight lines of four
bytes to facilitate data transfer across BBus. Both the transmit and receive FIFOs are
accessed using the Serial Channel B/A/C/D FIFO registers.
Transmit FIFO interface
The processor can write either 1, 2, 3, or 4 bytes at a time to the transmit FIFO. The
number of bytes written is controlled by the data size defined by the
HSIZE
field on
the AMBA AHB bus.
When the system is configured to operate in big endian mode, the most
significant bytes in the word written to the FIFO are transmitted first. For
example, the long word
0x11223344
results in the character
0x11
being
transmitted first, and
0x44
being transmitted last.