Digi NS9750 - Manual (Page 15)

x i i i
LCDPalette register.............................................................595
Interrupts ...............................................................................598
MBERRORINTR — Master bus error interrupt................................598
VCOMPINTR — Vertical compare interrupt..................................598
LBUINTR — Next base address update interrupt ...........................599
C h a p t e r 1 3 : S e r i a l C o n t r o l M o d u l e : U A R T ........................................... 601
Features.................................................................................602
Bit-rate generator ..............................................................603
UART mode .............................................................................604
FIFO management ....................................................................605
Transmit FIFO interface .......................................................605
Receive FIFO interface.........................................................606
Serial port performance ..............................................................608
Serial port control and status registers ............................................608
Serial Channel B/A/C/D Control Register A ................................611
Serial Channel B/A/C/D Control Register B ................................614
Serial Channel B/A/C/D Status Register A ..................................617
Serial Channel B/A/C/D Bit-rate register ...................................624
Serial Channel B/A/C/D FIFO Data register ................................629
Serial Channel B/A/C/D Receive Buffer GAP Timer .......................630
Serial Channel B/A/C/D Receive Character GAP Timer ..................632
Serial Channel B/A/C/D Receive Match register...........................634
Serial Channel B/A/C/D Receive Match MASK register ...................635
Serial Channel B/A/C/D Flow Control register.............................636
Serial Channel B/A/C/D Flow Control Force register .....................638
C h a p t e r 1 4 : S e r i a l C o n t r o l M o d u l e : S P I .................................................. 643
Features.................................................................................644
Bit-rate generator ..............................................................645
SPI mode ................................................................................646
SPI modes ........................................................................646
FIFO management .....................................................................647
Transmit FIFO interface .......................................................647
Receive FIFO interface.........................................................648
Serial port performance ..............................................................650