Digi NS9750 - Manual (Page 411)

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E t h e r n e t C o m m u n i c a t i o n M o d u l e
Ethernet Interrupt Enable register
Address: A060 0A14
The Ethernet Interrupt Enable register contains individual enable bits for each of the
bits in the Ethernet Interrupt Status register. When these bits are cleared, the
corresponding bit in the Ethernet Interrupt Status register cannot cause the interrupt
signal to the system to be asserted when it is set.
D06 R/C STOVFL 0 Assigned to TX interrupt.
Statistics counter overflow. Individual counters can
be masked using the Carry Register 1 and 2 Mask
registers. The source of this interrupt is cleared by
clearing the counter that overflowed, and by clearing
the associated carry bit in either Carry Register 1 or
Carry Register 2 by writing a 1 to the bit.
D05 R Not used 0 Always write as 0.
D04 R/C TXBUFC 0 Assigned to TX interrupt.
I bit set in the Transmit Buffer Descriptor and buffer
closed.
D03 R/C TXBUFNR 0 Assigned to TX interrupt.
F bit not set in the Transmit Buffer Descriptor when
read from the TX Buffer descriptor RAM.
D02 R/C TXDONE 0 Assigned to TX interrupt.
Frame transmission complete.
D01 R/C TXERR 0 Assigned to TX interrupt.
Last frame not transmitted successfully. See "Ethernet
Interrupt Status register" on page 385 for information
about restarting the transmitter when this bit is set.
D00 R/C TXIDLE 0 Assigned to TX interrupt.
TX_WR logic has no frame to transmit. See "Ethernet
Interrupt Status register" on page 385 for information
about restarting the transmitter when this bit is set.
Bits Access Mnemonic Reset Description
Table 240: Ethernet Interrupt Status register