Digi NS9750 User Manual
Page 198
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D y n a m i c m e m o r y c o n t r o l l e r
1 7 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Table 103 shows the outputs from the memory controller and the corresponding
inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
6
6
20
8
5
5
19
7
4
4
18
6
3
3
17
5
2
2
16
4
1
1
15
3
0
0
14
2
Output address
(
ADDROUT
)
Memory device
connections
AHB address to row
address
AHB address to
column address
14
BA1
13
13
13
BA0
14
14
12
12
27
-
11
11
26
12
10
10/AP
25
AP
9
9
24
11
8
8
23
10
7
7
22
9
6
6
21
8
5
5
20
7
4
4
19
6
3
3
18
5
2
2
17
4
Table 103: Address mapping for 512M SDRAM (64Mx8, RBC)
Output address
(
ADDROUT
)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 102: Address mapping for 512M SDRAM (32Mx16, RBC)
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