Digi NS9750 User Manual
Page 5
Contents
i i i
C h a p t e r 1 :
A b o u t N S 9 7 5 0
............................................................................................... 1
NS9750 Features ......................................................................... 2
System-level interfaces................................................................. 8
System boot ............................................................................. 10
Reset...................................................................................... 10
RESET_DONE as an input........................................................ 11
RESET_DONE as an output ...................................................... 11
System clock............................................................................. 13
USB clock................................................................................. 15
C h a p t e r 2 :
N S 9 7 5 0 P i n o u t
........................................................................................... 17
Pinout and signal descriptions ........................................................ 18
System Memory interface ...................................................... 18
System Memory interface signals.............................................. 22
Ethernet interface............................................................... 25
Clock generation/system pins ................................................. 26
bist_en_n, pll_test_n, and scan_en_n ........................................ 28
PCI interface...................................................................... 28
GPIO MUX ......................................................................... 34
LCD module signals .............................................................. 42
I2C interface...................................................................... 43
USB interface ..................................................................... 43
JTAG interface for ARM core/boundary scan................................ 43
Reserved .......................................................................... 45
Power ground..................................................................... 46