Digi NS9750 - Manual (Page 601)

w w w . d i g i e m b e d d e d . c o m 5 7 7
L C D C o n t r o l l e r
Table 347 shows which
CLD[23:0]
pins are used to provide the pixel data to the TFT
panel for each mode of operation.
CLD[7] AE8=LCD data bit 7 (O1) CUSTN[0] 1 CUSTN[0] 1 N/A N/A MUSTN[0] MUSTN[0] 1
CLD[6] AD9=LCD data bit 6 (O1) CUSTN[1] CUSTN[1] N/A N/A MUSTN[1] MUSTN[1]
CLD[5] AF8=LCD data bit 5 (O1) CUSTN[2] CUSTN[2] N/A N/A MUSTN[2] MUSTN[2]
CLD[4] AE9=LCD data bit 4 (O1) CUSTN[3] CUSTN[3] N/A N/A MUSTN[3] MUSTN[3]
CLD[3] AF9=LCD data bit 3 (O1) CUSTN[4] CUSTN[4] MUSTN[0] MUSTN[0]
1
MUSTN[4] MUSTN[4]
CLD[2] AD10=LCD data bit 2 (O1) CUSTN[5] CUSTN[5] MUSTN[1] MUSTN[1] MUSTN[5] MUSTN[5]
CLD[1] AE10=LCD data bit 1 (O1) CUSTN[6] CUSTN[6] MUSTN[2] MUSTN[2] MUSTN[6] MUSTN[6]
CLD[0] AF10=LCD data bit 0 (O1) CUSTN[7] CUSTN[7] MUSTN[3] MUSTN[3] MUSTN[7] MUSTN[7]
1 This data bit corresponds to the first “pixel position.” For example, for an 8-bit mono STN display, CUSTN[0] is the
leftmost pixel on the panel and CUSTN[7] is the rightmost pixel within the 8-bit data. For a color STN display, bits [7,
6, 5] form the leftmost pixel.
Ext
pin GPIO pin & description
Color
STN
single
panel
Color
STN dual
panel
4-bit
mono
STN
single
panel
4-bit
mono
STN dual
panel
8-bit
mono
STN
single
panel
8-bit
mono
STN dual
panel
Table 346: LCD STN panel signal multiplexing
External pin TFT 24 bit TFT 15 bit
CLD[23] Blue[7] Reserved
CLD[22] Blue[6] Reserved
CLD[21] Blue[5] Reserved
CLD[20] Blue[4] Reserved
CLD[19] Blue[3] Reserved
CLD[18] Blue[2] Reserved
CLD[17] Blue[1] Blue[4]
CLD[16] Blue[0] Blue[3]
Table 347: LCD TFT panel signal multiplexing