Digi NS9750 - Manual (Page 460)

P C I b u s a r b i t e r
4 3 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
D13 R/W PRXMAEN 0 PCI received master abort enable
0 Interrupt disabled
1 Interrupt enabled
Bit 13 of PCI Status register
D12 R/W PRXTARN 0 PCI received target abort enable
0 Interrupt disabled
1 Interrupt enabled
Bit 12 of PCI Status register
D11 R/W PSIGTAEN 0 PCI signaled target abort enable
0 Interrupt disabled
1 Interrupt enabled
Bit 11 of PCI Status register
D10:09 Hardwired to
0 Reserved N/A N/A
D08 R/W PMPERREN 0 PCI master data parity error enable
0 Interrupt disabled
1 Interrupt enabled
Bit 8 of PCI Status register
D07:01 Hardwired to
0 Reserved N/A N/A
D00 R/W AHBERREN 0 AHB bus error enable
0 Interrupt disabled
1 Interrupt enabled
Bit 0 of PCI Bridge Interrupt Status register
Bits Access Mnemonic Reset Description
Table 272: PCI Bridge Interrupt Enable register