Digi NS9750 - Manual (Page 288)

P r o g r a m m a b l e t i m e r s
2 6 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
in the appropriate Timer Control register (see "Timer 0–15 Control registers" on page
301).
With a 16-bit counter and a 16-bit prescaler, each GPTC can measure external event
length up to minutes in range, and can be individually enabled or disabled. GPTCs can
be configured to reload, with the value defined in the appropriate Timer Reload
Count register (see page 284), and generates an interrupt upon terminal count. Each
GPTC has an interrupt request connected to the IRQ vector interrupt controller (VIC).
The priority level and enable/disable of each interrupt can be programmed in the
VIC, and the contents of the timer/counter can be read by the CPU.
The GPTCs can be concatenated to form counters for longer time scales.
These control fields should be in the control register of each GPTC:
Clock frequency selection
Mode of operation:
–
Internal timer, with or without external terminal count indicator
–
External gated timer with gate active low
–
External gated timer with gate active high
–
External event counter; frequency must be less than one half the CPU clock
frequency
Timer/counter enable
Count up or down
Interrupt enable
Concatenate to upstream timer/counter. That is, use upstream timer/
counter’s overflow/underflow output as clock input (16- or 32-bit timer/
counter).
Reload enable
Debug mode
The 16 timers/counters continue to run when the debugger halts the CPU in debug
mode. This is not a problem in normal operation.
There is a script available that causes the debugger to continually reset one or more
timers while the CPU is halted. Use this debugger script to work around this issue.