Digi NS9750 - Manual (Page 503)

w w w . d i g i e m b e d d e d . c o m 4 7 9
B B u s B r i d g e
Figure 81: Peripheral DMA burst write access
Peripheral REQ signaling
An external peripheral indicates that it can accept or provide data by asserting its
REQ signal. The AHB DMA controller fully processes one buffer descriptor for each
assertion of the external peripheral’s REQ signal.
The AHB DMA controller state machine executes these steps for each assertion of the
REQ signal.
1
Fetch the next buffer descriptor in the list from system memory.
2
Read the number of bytes specified in the buffer length field from the address
specified in the source address field. This data is placed in an on-chip temporary
buffer.
3
Write the data from the on-chip temporary buffer to the address specified in the
source address field.
4
Retire the buffer descriptor to system memory.
5
Assert any specified interrupts to the CPU.
6
Return to the idle condition and wait for the next assertion of the external
peripheral’s REQ signal.
For memory-to-memory DMA transfers that are initiated by software writing a 1 to
the CG field in the DMA Channel 1/2 Control register, the peripheral signal
REQ
is
ignored.
CLK
DATA0 DATA1 DATA2
CS#
W E#
DQ