Digi NS9750 - Manual (Page 142)

F e a t u r e s
1 1 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Low-power operation
In many systems, the contents of the memory system have to be maintained during
low-power sleep modes. NS9750 provides two features to enable this:
Dynamic memory refresh over soft reset
A mechanism to place the dynamic memories into self-refresh mode
Self-refresh mode can be entered as follows:
1
Set the SREFREQ bit in the Dynamic Memory Control register (see page 208).
2
Poll the SREFACK bit in the Status register (see page 207).
Note:
Static memory can be accessed as normal when the SDRAM memory is in
self-refresh mode.
Low-power SDRAM partial array refresh
The memory controller supports JEDEC low-power SDRAM partial array refresh.
Partial array refresh can be programmed by initializing the SDRAM memory device
appropriately. When the memory device is put into self-refresh mode, only the
memory banks specified are refreshed. The memory banks that are not refreshed lose
their data contents.
Memory map
The memory controller provides hardware support for booting from external
nonvolatile memory. During booting, the nonvolatile memory must be located at
address
0x00000000
in memory. When the system is booted, the SRAM or SDRAM memory
can be remapped to address
0x00000000
by modifying the address map in the AHB
decoder.
Power-on reset memory map
On power-on reset, memory chip select 1 is mirrored onto memory chip select 0 and
chip select 4. Any transactions to memory chip select 0 or chip select 4 (or chip
select 1), then, access memory chip select 1. Clearing the address mirror bit (M) in
the Control register (see page 205) disables address mirroring, and memory chip
select 0, chip select 4, and memory chip select 1 can be accessed as normal.