Digi NS9750 User Manual

Page 280

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S y s t e m b u s a r b i t e r

2 5 6

N S 9 7 5 0 H a r d w a r e R e f e r e n c e

Main arbiter. Contains a 16-entry Bus Request Configuration (BRC) register.
Each BRC entry represents a bus request and grant channel. Each request/
grant channel can be assigned to only one bus master at a time. Each bus
master can be connected to multiple request/grant channels
simultaneously, however, depending on the bus bandwidth requirement of
that master.
Each request/grant channel has a two-bit Bandwidth Reduction Field (BRF)
to determine how often each channel can arbitrate for the system bus —
100%, 75%, 50%, or 25%. A BRF value of 25%, for example, causes a channel
to be skipped every 3 or 4 cycles. The BRC gates the bus requesting signals
going into a 16-entry Bus Request register (BRR). As a default, unassigned
channels in the BRC block the corresponding BRR entries from being set by
any bus request signals. On powerup, only the CPU is assigned to one of the
channels with 100% bandwidth strength as the default setting.

How the bus arbiter works

1

The arbiter evaluates the Bus Request register at every bus clock until one or
more bus requests are registered.

2

The arbiter stops evaluating the Bus Request register until a bus grant is issued
for the previous evaluation cycle.

3

The arbiter grants the bus to requesting channels, in a round-robin manner, at
the rising clock edge of the last address issued for the current transaction (note
that each transaction may have multiple transfers), when a SPLIT response is
sampled by the arbiter, or when the bus is idling.

4

Each master samples the bus grant signal (

hgrant_x

) at the end of the current

transfer, as indicated by the

hready

signal. The bus master takes ownership of the

bus at this time.

5

The arbiter updates the

hmaster [3:0]

signals at the same time to indicate the

current bus master and to enable the new master’s address and control signals
to the system bus.

See your AMBA standards documentation for detailed information and illustrations of
AMBA AHB transactions.

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