Digi NS9750 - Manual (Page 367)

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E t h e r n e t C o m m u n i c a t i o n M o d u l e
D03 R/W TCLER 0 Clear transmit error
0->1 transition: Clear transmit error.
Clears out conditions in the transmit packet processor that
have caused the processor to stop and require assistance
from software before the processor can be restarted (for
example, an AHB bus error or the TXBUFNR bit set in the
Ethernet Interrupt Status register (see page 385)).
Toggle this bit from low to high to restart the transmit
packet processor.
D02 R/W AUTOZ 0 Enable statistics counter clear on read
0 No change in counter value after read
1 Counter cleared after read
When set, configures all counters in the Statistics module
to clear on read.
If AUTOZ is not set, the counters retain their value after a
read. The counters can be cleared by writing all zeros.
D01 R/W CLRCNT 1 Clear statistics counters
0 Do not clear all counters
1 Clear all counters
When set, synchronously clears all counters in the
Statistics module.
D00 R/W STEN 0 Enable statistics counters
0 Counters disabled
1 Counters enabled
When set, enables all counters in the Statistics module. If
this bit is cleared, the counters will not update.
Bits Access Mnemonic Reset Description
Table 207: Ethernet General Control Register #2