Digi NS9750 - Manual (Page 12)

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CardBus interrupts..............................................................465
C h a p t e r 8 : B B u s B r i d g e ................................................................................................467
BBus bridge functions .................................................................468
Bridge control logic ...................................................................469
DMA accesses ....................................................................471
BBus control logic .....................................................................472
BBus bridge masters and slaves...............................................472
Cycles and BBus arbitration ...................................................473
BBus peripheral address map (decoding) ...................................473
Two-channel AHB DMA controller (AHB bus) ......................................474
DMA buffer descriptor..........................................................474
Descriptor list processing......................................................476
Peripheral DMA read access...................................................477
Peripheral DMA write access ..................................................478
Peripheral REQ signaling.......................................................479
Design Limitations ..............................................................480
Calculating AHB DMA response latency......................................480
Static RAM chip select configuration ........................................482
Interrupt aggregation .................................................................483
Bandwidth requirements .............................................................483
SPI-EEPROM boot logic ................................................................484
Serial Channel B configuration ...............................................485
Memory Controller configuration.............................................486
SDRAM boot algorithm .........................................................488
BBus Bridge Control and Status registers ..........................................490
Buffer Descriptor Pointer register ...........................................491
DMA Channel 1/2 Control register ...........................................491
DMA Status and Interrupt Enable register...................................494
DMA Peripheral Chip Select register .........................................496
BBus Bridge Interrupt Status register........................................498
BBus Bridge Interrupt Enable register .......................................499
C h a p t e r 9 : B B u s D M A C o n t r o l l e r ......................................................................501
About the BBus DMA controllers.....................................................502
DMA context memory .................................................................503